MODELSIM WAVEFORM HOW TO
See how to install the free student edition of ModelSim here Waveform with delta cycles expanded Remember to restart ModelSim after changing the ini file. The modelsim.ini file is located in the folder where you installed ModelSim. To make ModelSim show all delta cycles, “WLFCollapseMode = 0” must be set in the modelsim.ini file as shown below. You will not be able to see beyond delta cycle +1 without changing the configuration file. Show all delta cycles in the ModelSim waveformīy default, ModelSim will only log an object’s value at the start and at the end of a timestep.
MODELSIM WAVEFORM SIMULATOR
Whenever a process is paused as the result of a Wait statement, the simulator keeps track of the future values of signals driven by that process and how long into the future it shall skip ahead before the next event is due to happen. For the above example, the event schedule will look like this: Simulation time This is possible because a delta cycle is a zero-time timestep.Īs the simulator executes the code, it will maintain an internal table of the next events that are scheduled to happen. Although we are still at 0 ns simulation time, the signal now has a new value. The signal was '0' at the start of the simulation but changes to '1' before any time has passed at all. In practice, the simulator will schedule the signal to have the new value in the next delta cycle. In VHDL, signal values are only updated when the process hits a Wait statement. Then, the simulator will run the process and stop at the wait for 5 ns line.
MODELSIM WAVEFORM CODE
Simulators use a technique called event scheduling to precisely model the behavior of VHDL code while doing the least amount of work.Īt the start of the simulation, Sig1 has its initial value of '0'. But how does this work internally in the simulator?
Every time a signal changes, it is an event. Unsurprisingly, Sig1 changes between '0' and '1' with a frequency of 100 MHz. This is the code from the previous example, but with an additional process that inverts the value of Sig1 every 5 nanoseconds: It is easy to know what the output will look like in a second or an hour from now, because it is exactly the same as now.įrom the simulator’s point of view, there are no events in this VHDL code. The Sig1 signal is '0' right from the start, and it doesn’t change at all.
There is not a lot going on in this code. How can it be that this very long simulation completed so fast? VSIM 1> run 200 hr VSIM 2> When I tell ModelSim to simulate this design for 200 hours, that works just fine, in fact, the simulation completes almost instantly, and the command prompt gives me a new line where I can enter the next command. Let’s first look at what happens when we run this trivial VHDL code in the ModelSim VHDL simulator: To precisely model the behavior of digital logic, simulators use an event-based approach for executing VHDL code. While in VHDL, there can be multiple sequences of logic that react to each other in ways that are not compatible with the standard computer architecture. When a normal programming language is run, the CPU executes one instruction after the other. VHDL is a parallel programming language, while computers and CPUs work in a sequential manner. They are events that happen in zero simulation time after a preceding event. Delta cycles are non-time-consuming timesteps used by VHDL simulators for modeling events during execution of VHDL code.
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